High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory.
Operation frequency of low-power dynamic random-access memory (LPDRAM) has doubled for each generation, and the data (e.g., prefetch) to be simultaneously accessed by a READ command or a WRITE command has also doubled as in the operation frequency. For example, in the case of a low-power double data rate 3 (LPDDR3) type synchronous DRAM (SDRAM) with an operation frequency of 1.6 Gbps and a word line having a word length of 1 Kb (=1024 bits), sixty-four bits are read from the word line in a READ operation, and sixty-four bits are written in one WRITE operation; however, the latest low-power SDRAM, such as a low-power double data rate 4 (LPDDR4) type facilitates 128 bits data access through a word line having a word length of 1 KB.
Such low-power type memory may have a general three-layered metal configuration. Metal wires of lower layers can be used as wires which have the same pitch as memory cells. For example, metal wires on the first layer of lower layers may be used for column select signals (YS) and metal wires on the second layer of the lower layers may be used for main word lines. Main input/output lines (MIO) may be metal wires, such as the third level aluminum interconnection (3AL), on the uppermost layer in order to couple peripheral read amplifiers and write buffer circuits to local IO lines (LIO) within the array. Due to the doubling of data provided per access, more metal wires may be included on the uppermost layer. The uppermost layer may also include power supply lines to distribute power supplies to all over the memory. Due to the increased number of wires for data access, the width of metal wires for the power supply may be reduced. This reduction of the width of metal wires for the power supply may result in deteriorating an operation margin due to a decrease of a power level when multiple operations are executed simultaneously.